1. Field of the Invention
This invention relates to an electronic device and a method for manufacturing electronic parts, and more particularly is applicable to a multichip module and a method for manufacturing the multichip module.
2. Description of the Related Art
Conventionally, as such electronic device, there has been known a multichip module in which a plurality of chip parts are mounted with high density on a multilayer wiring substrate and an entire body is thus made compact, so that the wiring length between the respective chip parts can be relatively shortened and the high speed characteristic and high frequency characteristic or the like of the respective chip parts can be improved.
As illustrated in FIG. 1, a multichip module 1 ordinarily comprises a multilayer wiring substrate 2 formed by sequentially laminating and forming insulating layers composed of ceramic substrates or organic substrates or the like and wiring layers having prescribed conductor patterns in the direction of its thickness, a plurality of chip parts 3 formed on one surface 2A of the multilayer wiring substrate 2, and protrusion electrodes 4 (referred to as soldering bumps, hereinafter) obtained by soldering a plurality of pads (not shown) respectively formed on circuit surfaces 3A of corresponding lands (not shown) on the multilayer wiring substrate 2. The respective chip parts 3 are electrically and physically connected to and mounted on the one surface 2A of the multilayer wiring substrate 2 through the soldering bumps 4.
In this connection, in the multichip module 1, since the coefficient of thermal expansion of the multilayer wiring substrate 2 has a value not smaller than two times the coefficient of thermal expansion of the chip parts 3, if the chip parts 3 generate heat owing to the operation of the chip parts 3 and so on, thermal stress may be concentrated on the respective soldering bumps 4 formed between the multilayer wiring substrate 2 and the respective chip parts 3, which may cause inconveniently the soldering bumps 4 to be broken.
For overcoming this disadvantage, in the above mentioned multichip module 1,spaces formed between the one surface 2A of the multilayer wiring substrate 2 and the circuit surfaces 3A of the respective chip parts 3 are respectively filled with an insulating material (namely, an underfilling material) 5 so as to embed the respective soldering bumps 4 therein. Thus, according to the above stated multichip module 1, the concentration of the thermal stress generated on the respective soldering bumps 4 can be mitigated because of the insulating material 5, so that the soldering bumps 4 can be prevented from being broken. Further, the insulating material 5 is designed to cover the respective circuit surfaces 3A of the chip parts 3 so that it can protect the circuit surfaces 3A from troubles due to impurities or moisture contained in outside air as well as can prevent the breakage of the respective soldering bumps 4.
In recent years, in the multichip module 1 described above, it has been desired that the construction of a multichip module 1 is made more compact, in order to mount the respective chip parts 3 on the one surface 2A of the multilayer wiring substrate 2 with a higher density.
However, according to the multichip module 1 in question, when the spaces between the respective chip parts 3 are narrowed in some degree or more, there have occurred problems that it is difficult to fill the spaces between the one surface 2A of the multilayer wiring substrate 2 and the respective circuit surfaces 3A of the chip parts 3 with the insulating material 5 so that the insulating material 5 hardly prevents the breakage of the respective soldering bumps 4, and that the circuit surfaces 3A of the respective chip parts 3 are seldom protected. Accordingly, when the respective chip parts 3 are mounted on the substrate with a higher density and the size of the multichip module 1 is made smaller, there has arisen a problem that quality and reliability of the multichip module 1 are disadvantageously degraded markedly.
In addition, in the above multichip module 1, when the number of the chip parts 3 mounted on the one surface 2A of the multilayer wiring substrate 2 is increased, a heat generation rate of the entire module depending on the operation of the respective chip parts 3 is also increased, so that the thermal stress converged to the respective soldering bumps 4, which results from the difference in the coefficient of thermal expansion between the multilayer wiring substrate 2 and the chip parts 3, is hardly lowered only by the insulating material 5. Therefore, in such a case, a method may be considered for mitigating the thermal stress concentrated onto the respective soldering bumps 4 by relatively enlarging the size of the respective bumps 4, in addition to the insulating material 5.
However, in the above mentioned case, the lands of the multilayer wiring substrate 2 have needed to be enlarged depending on the dimension of the soldering bumps 4, and therefore, the multilayer wiring substrate 2 has been undesirably made larger. In other words, the multilayer wiring substrate 27 has been enlarged, which has inconveniently caused the entire body of the multichip module 1 to be also enlarged.
Additionally, in the above described multichip module 1, when the number of the pads of the chip parts 3 mounted on the one surface 2A of the multilayer wiring substrate 2 is comparatively large, the number of wirings electrically connected to the lands of the multilayer wiring substrate 2 is also proportionally increased. Therefore, the number of wiring layers formed on the multilayer wiring substrate 2 must be increased.
In this case, however, since the insulating layers to be increased together with the wiring layers in the multilayer wiring substrate 2 has approximately 0.1 mm per layer, the multilayer wiring substrate 2 has been undesirably comparatively increased in its thickness.